It is known to bond an ASIC wafer to a MEMS device wafer to form a wafer-level chip scale package. In such an integrated wafer-level chip scale package, the ASIC wafer is effectively the cap wafer. Depending on the bond seal material thickness or patterned standoff depth, such devices often have a cavity depth on the order of approximately 2-4 micrometers (abbreviated “um” herein). In such devices, the close proximity of MEMS device structures to the ASIC circuitry can result in the MEMS device structures contributing time-varying parasitic capacitance and impedance cross-talk to the circuits that are spaced only a few micrometers away on the ASIC wafer.